1. Field of the Invention
This invention relates to a semiconductor memory device, and particularly to a synchronous DRAM (Dynamic Random Access Memory) for outputting control signals for read and write operations, each of which is synchronized with a clock pulse.
2. Description of the Related Art
A synchronous DRAM (hereinafter called "SDRAM") is known as a high-speed operable DRAM. An SDRAM of an address-increment pipeline scheme system disclosed in "1994 Symposium on VLSI Circuits Digest of Technical Papers" published from IEEE, 1994, pages 81-82 has been proposed as this type of SDRAM.
In the conventional SDRAM, a column address signal is latched in a first stage, data read from a memory array supplied with the column address signal is latched in a second stage. In the subsequent third stage, the read data is outputted through an output buffer activated with an external clock as a trigger.
In such a pipeline process, the respective stages need to be distributed to even or uniform numbers of clock pulses respectively. A clock frequency is considered to increase in order to achieve the high-speed operation. However, the operation of the first stage requiring the longest processing time interferes with the increase in clock frequency. Therefore, the memory array is divided into two arrays to achieve the high-speed operation in the above-described scheme system. Further, the first stage is divided into two blocks for purposes of the divided two arrays. In the divided individual blocks of the first stage, the reading of data from the divided individual arrays corresponding to the respective blocks is processed in parallel to achieve the high-speed operation.
In the conventional SDRAM, however, the time between latching the column address signal, i.e., inputting the address signal to the memory array and reading data from the memory array requiring the longest processing time subsequent to its input is basically controlled in synchronism with the clock.
Therefore, the length of the processing time between the input of the address signal to the memory array and the reading of the data from the memory array has no flexibility.
In the conventional SDRAM as is understood from this point of view, when the frequency of a master clock is being set to, e.g., 125 MHz (clock cycle is being set to 8 ns), a high-speed operation at 125 MHz or more cannot be achieved even if the processing in the first stage is done in a cycle less than or equal to this clock cycle.